This invention pertains to latch circuits and, in particular, direct-coupled FET logic (DCFL) latch circuits.
Latch circuits are utilized in numerous applications. A latch circuit typically consists of an acquire stage and a regeneration stage where data is clocked into the acquire stage when the clock is in a first logic state and then stored in the regeneration stage when the clock is in a second logic state, as is known. Most, if not all, DCFL technology has utilized two separate load devices: one for providing current to the acquire stage and another for providing current to the regeneration stage. Furthermore, since each load device typically draws a predetermined current, the power of most FET (field-effect transistor) circuits is directly proportional to the number of load devices used therein. Therefore, if a single load device could be shared between two different field-effect transistors (FET's), a substantial power reduction would result along with a decrease in device count.
Hence, a need exists for a DCFL latch circuit having minimum power and minimum device count.